Invention Grant
- Patent Title: Wafer level chip scale package having varying thicknesses
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Application No.: US16874392Application Date: 2020-05-14
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Publication No.: US11721657B2Publication Date: 2023-08-08
- Inventor: Jing-En Luan
- Applicant: STMICROELECTRONICS PTE LTD
- Applicant Address: SG Singapore
- Assignee: STMICROELECTRONICS PTE LTD
- Current Assignee: STMICROELECTRONICS PTE LTD
- Current Assignee Address: SG Singapore
- Agency: Seed IP Law Group LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498

Abstract:
A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.
Information query
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