Invention Grant
- Patent Title: Methods of reducing clock domain crossing timing violations, and related devices and systems
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Application No.: US17369055Application Date: 2021-07-07
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Publication No.: US11727979B2Publication Date: 2023-08-15
- Inventor: Kallol Mazumder , Navya Sri Sreeram , William C. Waldrop , Vijayakrishna J. Vankayala
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C11/4076 ; G11C11/4096 ; G06F3/06 ; G11C7/10

Abstract:
Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.
Public/Granted literature
- US20230007872A1 METHODS OF REDUCING CLOCK DOMAIN CROSSING TIMING VIOLATIONS, AND RELATED DEVICES AND SYSTEMS Public/Granted day:2023-01-12
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