Invention Grant
- Patent Title: Package substrate and semiconductor package including the same
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Application No.: US17183513Application Date: 2021-02-24
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Publication No.: US11728283B2Publication Date: 2023-08-15
- Inventor: Chilwoo Kwon , Jeongseok Kim , Junggon Choi
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Muir Patent Law, PLLC
- Priority: KR 20200099633 2020.08.10
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/10 ; H01L23/31 ; H01L23/538 ; H01L23/64

Abstract:
A package substrate may include a plurality of stacked insulation layers, a plurality of RDLs and a pair of impedance patterns. The RDLs may be arranged between the insulation layers. The impedance patterns may be arranged on an upper surface of at least one of the insulation layers. The impedance patterns may have an insulation length corresponding to a summed length of thicknesses of at least two insulation layers among the plurality of the insulation layers. Thus, a dummy conductive pattern may not be arranged between the impedance patterns and the RDL so that only the insulation layer may exist between the impedance patterns and the RDL. As a result, the insulation length of the impedance patterns may correspond to the summed length of the thicknesses of the at least two insulation layers.
Information query
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