Semiconductor package, and package on package having the same

    公开(公告)号:US11581263B2

    公开(公告)日:2023-02-14

    申请号:US17024852

    申请日:2020-09-18

    Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

    Semiconductor package
    2.
    发明授权

    公开(公告)号:US11043446B2

    公开(公告)日:2021-06-22

    申请号:US16662360

    申请日:2019-10-24

    Abstract: A semiconductor package includes a connection structure including a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a first connection via penetrating through the first insulating layer and connected to the first redistribution layer, a semiconductor chip disposed on the connection structure, an encapsulant covering at least a portion of the semiconductor chip, a second insulating layer disposed on the encapsulant, a second redistribution layer including a signal line disposed on the encapsulant, and a heat dissipation layer disposed on the encapsulant and electrically insulated from the signal line.

    SEMICONDUCTOR PACKAGE, AND PACKAGE ON PACKAGE HAVING THE SAME

    公开(公告)号:US20210257305A1

    公开(公告)日:2021-08-19

    申请号:US17024852

    申请日:2020-09-18

    Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

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