Invention Grant
- Patent Title: Semiconductor wafer fault analysis system and operation method thereof
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Application No.: US16599733Application Date: 2019-10-11
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Publication No.: US11741596B2Publication Date: 2023-08-29
- Inventor: Min-Chul Park , Ami Ma , Jisu Ryu , Changwook Jeong
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Lee IP Law, P.C.
- Priority: KR 20180153781 2018.12.03
- Main IPC: G06K9/00
- IPC: G06K9/00 ; G06T7/00 ; H01L21/67 ; G01N21/956 ; G01N21/95 ; G06T5/00 ; G01N21/88 ; G06V10/70 ; G06V10/82 ; G06V10/74

Abstract:
A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.
Public/Granted literature
- US20200175665A1 SEMICONDUCTOR WAFER FAULT ANALYSIS SYSTEM AND OPERATION METHOD THEREOF Public/Granted day:2020-06-04
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