- 专利标题： Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors
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申请号： US17502210申请日： 2021-10-15
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公开(公告)号： US11742246B2公开(公告)日： 2023-08-29
- 发明人: Ruilong Xie , Hemanth Jagannathan , Christopher J. Waskiewicz , Alexander Reznicek
- 申请人： International Business Machines Corporation
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Fleit Intellectual Property Law
- 代理商 Thomas S. Grzesik
- 分案原申请号： US16528748 2019.08.01
- 主分类号： H01L21/8234
- IPC分类号： H01L21/8234 ; H01L27/088 ; H01L29/78 ; H01L29/66 ; H01L21/762
摘要：
A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.
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