Invention Grant
- Patent Title: Method of forming an array of multi-stack nanosheet structures having a dam structure isolating multi-stack transistors
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Application No.: US17866066Application Date: 2022-07-15
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Publication No.: US11742345B2Publication Date: 2023-08-29
- Inventor: Inchan Hwang , Hwichan Jun
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L27/085 ; H01L21/8234

Abstract:
An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.
Public/Granted literature
- US20220359500A1 ARRAY OF MULTI-STACK NANOSHEET STRUCTURES Public/Granted day:2022-11-10
Information query
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