- Patent Title: Gate-all-around integrated circuit structures having oxide sub-fins
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Application No.: US16238783Application Date: 2019-01-03
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Publication No.: US11742410B2Publication Date: 2023-08-29
- Inventor: Leonard P. Guler , Biswajeet Guha , Tahir Ghani , Swaminathan Sivakumar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/66 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L21/02 ; H01L21/306

Abstract:
Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.
Public/Granted literature
- US20200219978A1 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS Public/Granted day:2020-07-09
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