Invention Grant
- Patent Title: Command address input buffer bias current reduction
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Application No.: US17409495Application Date: 2021-08-23
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Publication No.: US11748035B2Publication Date: 2023-09-05
- Inventor: Gary L. Howe
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G11C11/00 ; G06F3/06 ; G11C11/408 ; G11C11/4096 ; G11C7/10 ; B24D18/00 ; B32B3/30 ; B32B13/06 ; E21B10/567 ; E21B10/573 ; G11C11/4076 ; G11C8/12

Abstract:
A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.
Public/Granted literature
- US20210394339A1 COMMAND ADDRESS INPUT BUFFER BIAS CURRENT REDUCTION Public/Granted day:2021-12-23
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