- 专利标题: Flip-flop with input and output select and output masking that enables low power scan for retention
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申请号: US17517054申请日: 2021-11-02
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公开(公告)号: US11750178B2公开(公告)日: 2023-09-05
- 发明人: Thomas Saroshan David
- 申请人: Silicon Laboratories Inc.
- 申请人地址: US TX Austin
- 专利权人: Silicon Laboratories Inc.
- 当前专利权人: Silicon Laboratories Inc.
- 当前专利权人地址: US TX Austin
- 代理机构: Huffman Law Group, PC
- 代理商 Gary Stanford
- 主分类号: H03K3/356
- IPC分类号: H03K3/356 ; H03K3/012 ; H03K3/037
摘要:
A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.
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