Invention Grant
- Patent Title: Calibrated linear duty cycle correction
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Application No.: US17482336Application Date: 2021-09-22
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Publication No.: US11750185B2Publication Date: 2023-09-05
- Inventor: Siva Charan Nimmagadda , Xiaobao Wang , Vinit Shah , Sabarathnam Ekambaram , Hari Bilash Dubey
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H03K5/156
- IPC: H03K5/156 ; H03K5/134 ; H03K5/135 ; G11C7/22

Abstract:
Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.
Public/Granted literature
- US20230086781A1 CALIBRATED LINEAR DUTY CYCLE CORRECTION Public/Granted day:2023-03-23
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