An integrated circuit includes a backend thin-film transistor (TFT) a ferroelectric capacitor electrically connected to the backend TFT. The backend TFT has a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, and a gate dielectric between the gate electrode and semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals. In an embodiment, a memory cell includes this integrated circuit, the gate electrode being electrically connected to a wordline, the source region being electrically coupled to a bitline, and the drain region being the one of the source and drain regions. In an embodiment, an embedded memory includes wordlines, bitlines, and a plurality of such memory cells at crossing regions of the wordlines and bitlines.