Invention Grant
- Patent Title: Translation system for finer grain memory architectures
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Application No.: US17685212Application Date: 2022-03-02
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Publication No.: US11755515B2Publication Date: 2023-09-12
- Inventor: Brent Keeth , Richard C. Murphy , Elliott C. Cooper-Balis
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F13/28
- IPC: G06F13/28 ; G06F12/10 ; G06F13/16 ; G06F3/06 ; G06F12/1027 ; H01L23/538 ; H01L25/065 ; H01L25/18

Abstract:
Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
Public/Granted literature
- US20220188253A1 TRANSLATION SYSTEM FOR FINER GRAIN MEMORY ARCHITECTURES Public/Granted day:2022-06-16
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