In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.