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130 条记录 (耗时 0.03 秒)

    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING
    1.
    发明公开
    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING 审中-公开

    公开(公告)号：US20240331771A1

    公开(公告)日：2024-10-03

    申请号：US18741201

    申请日：2024-06-12

    申请人： Taiwan Semiconductor Manufacturing Company Ltd.

    发明人： Meng-Sheng Chang ,  Chia-En HUANG ,  Yi-Ching LIU ,  Yih WANG

    IPC分类号： G11C13/00

    CPC分类号： G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

    摘要： Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

    NOVEL VOLTAGE PROVISION CIRCUITS WITH CORE TRANSISTORS
    5.
    发明公开
    NOVEL VOLTAGE PROVISION CIRCUITS WITH CORE TRANSISTORS 审中-公开

    公开(公告)号：US20240146305A1

    公开(公告)日：2024-05-02

    申请号：US18170408

    申请日：2023-02-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ting-Yu Yu ,  Meng-Sheng Chang ,  Shao-Yu Chou

    IPC分类号： H03K19/0185 ,  H03K19/20

    CPC分类号： H03K19/018521 ,  H03K19/20

    摘要： The present disclosure includes a voltage provision circuit. In one aspect of the present disclosure, a voltage provision circuit is disclosed. The voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage. The voltage provision circuit includes a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage. The voltage provision circuit includes a first PMOS transistor sourced with a first supply voltage. The voltage provision circuit includes a second PMOS transistor sourced with the first supply voltage. The voltage provision circuit includes a voltage modulation circuit, coupled between the first to second PMOS transistors and the first to second NMOS transistors, that is configured to provide a first intermediate signal based on the first and second control signals. In some embodiments, the first intermediate signal has a first logic state corresponding to the first supply voltage and a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.

    Semiconductor memory devices with dielectric fin structures
    6.
    发明授权
    Semiconductor memory devices with dielectric fin structures 有权

    公开(公告)号：US11950411B2

    公开(公告)日：2024-04-02

    申请号：US17473636

    申请日：2021-09-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Meng-Sheng Chang ,  Chia-En Huang

    IPC分类号： H01L27/112 ,  H01L29/06 ,  H10B20/20

    CPC分类号： H10B20/20 ,  H01L29/0665

    摘要： A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.

    Novel Bank Design with Differential Bulk Bias in eFuse array
    10.
    发明公开
    Novel Bank Design with Differential Bulk Bias in eFuse array 审中-公开

    公开(公告)号：US20230377654A1

    公开(公告)日：2023-11-23

    申请号：US18362198

    申请日：2023-07-31

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Meng-Sheng Chang ,  Chia-En Huang

    IPC分类号： G11C16/04 ,  G11C17/16 ,  G11C16/12

    CPC分类号： G11C16/0483 ,  G11C17/165 ,  G11C16/12

    摘要： In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.