Invention Grant
- Patent Title: Thermal packaging with fan out wafer level processing
-
Application No.: US17663072Application Date: 2022-05-12
-
Publication No.: US11756861B2Publication Date: 2023-09-12
- Inventor: Ashley J. M. Erickson , Matthew J. Traverso , Sandeep Razdan , Joyce J. M. Peternel , Aparna R. Prasad
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cisco Technology, Inc.
- Current Assignee: Cisco Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- The original application number of the division: US16836825 2020.03.31
- Main IPC: H01L23/473
- IPC: H01L23/473 ; H01L21/48 ; H01L21/683 ; H01L23/00 ; H01L21/78 ; H01L23/544
Abstract:
An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.
Public/Granted literature
- US20220278022A1 THERMAL PACKAGING WITH FAN OUT WAFER LEVEL PROCESSING Public/Granted day:2022-09-01
Information query
IPC分类:
