公开(公告)号：US11373930B2

公开(公告)日：2022-06-28

申请号：US16836825

申请日：2020-03-31

Applicant: Cisco Technology, Inc.

Inventor： Ashley J. M. Erickson ,  Matthew J. Traverso ,  Sandeep Razdan ,  Joyce J. M. Peternel ,  Aparna R. Prasad

IPC: H01L23/473 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/78 ,  H01L23/544

Abstract: An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

公开(公告)号：US11215775B2

公开(公告)日：2022-01-04

申请号：US16544699

申请日：2019-08-19

Applicant: Cisco Technology, Inc.

Inventor： Ashley J. Maker ,  Joyce J. M. Peternel ,  Sandeep Razdan ,  Matthew J. Traverso ,  Aparna R. Prasad

IPC: G02B6/42

Abstract: An optical connection assembly joining optical components is described. The optical connection assembly is manufactured using a fan out wafer level packaging to produce dies/frames which include mechanical connection features. A fastener is joined to a connection component and affixed to the mechanical connection features, to provide structural support to the connection between the connected component and the die/frame structure.

公开(公告)号：US10145758B2

公开(公告)日：2018-12-04

申请号：US15582306

申请日：2017-04-28

Applicant: Cisco Technology, Inc.

Inventor： Matthew J. Traverso ,  Ravi S. Tummidi ,  Mark A. Webster ,  Sandeep Razdan

IPC: G01N21/00 ,  G01M11/00 ,  G02B6/12 ,  G02B6/13 ,  G02B6/122

Abstract: Embodiments herein describe techniques for testing optical components in a photonic chip using a testing structure disposed in a sacrificial region of a wafer. In one embodiment, the wafer is processed to form multiple photonic chips integrated into the wafer. While forming optical components in the photonic chips (e.g., modulators, detectors, waveguides, etc.), a testing structure can be formed in one or more sacrificial regions in the wafer. In one embodiment, the testing structure is arranged near an edge coupler in the photonic chip such that an optical signal can be transferred between the photonic chip and the testing structure. Moreover, the testing structure has a grating coupler disposed at or near a top surface of the wafer which permits optical signals to be transmitted into, or received from, the grating coupler when an optical probe is arranged above the grating coupler.

公开(公告)号：US11784175B2

公开(公告)日：2023-10-10

申请号：US17302853

申请日：2021-05-13

Applicant: Cisco Technology, Inc.

Inventor： Matthew J. Traverso ,  Sandeep Razdan ,  Ashley J. Maker

IPC: H01L23/00 ,  H01L25/16 ,  H01L31/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/167 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L31/02005 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.

公开(公告)号：US10962719B2

公开(公告)日：2021-03-30

申请号：US16260622

申请日：2019-01-29

Applicant: Cisco Technology, Inc.

Inventor： Sandeep Razdan ,  Ashley J. Maker ,  Jock T. Bovington ,  Matthew J. Traverso

IPC: G02B6/30

Abstract: Using laser patterning for an optical assembly, optical features are written into photonic elements at the end of a manufacturing sequence in order to prevent errors and damages to the optical features. The optical assembly is manufactured by affixing a photonic element to a substrate which includes one or more optical features and mapping one or more optical features for the photonic element. The optical features are then written into the fixed photonic element using laser patterning and the optical assembly is completed by connecting components, such as optical fibers, to the photonic element.

公开(公告)号：US11756861B2

公开(公告)日：2023-09-12

申请号：US17663072

申请日：2022-05-12

Applicant: Cisco Technology, Inc.

Inventor： Ashley J. M. Erickson ,  Matthew J. Traverso ,  Sandeep Razdan ,  Joyce J. M. Peternel ,  Aparna R. Prasad

IPC: H01L23/473 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L23/473 ,  H01L21/4803 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/544 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2224/32225

Abstract: An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

公开(公告)号：US11043478B2

公开(公告)日：2021-06-22

申请号：US15961163

申请日：2018-04-24

Applicant: Cisco Technology, Inc.

Inventor： Matthew J. Traverso ,  Sandeep Razdan ,  Ashley J. Maker

IPC: H01L23/00 ,  H01L25/16 ,  H01L31/02 ,  H01L23/498 ,  H01L21/48

Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.

公开(公告)号：US09964719B1

公开(公告)日：2018-05-08

申请号：US15582370

申请日：2017-04-28

Applicant: Cisco Technology, Inc.

Inventor： Sandeep Razdan ,  Vipulkumar Patel ,  Matthew J. Traverso

IPC: G02B6/42 ,  G02B6/138 ,  G02B6/34 ,  H01L21/56 ,  H01L23/00 ,  H01L25/16 ,  H01L21/768 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

CPC classification number: G02B6/4255 ,  G02B6/138 ,  G02B6/34 ,  G02B6/428 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/03 ,  H01L25/167 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/16145

Abstract: The present disclosure discloses an assembly. The assembly includes a photonic chip and an electrical chip disposed side by side. The assembly also includes mold compound that encapsulates the photonic chip and the electrical chip. The assembly further includes a redistribution layer (RDL) that extends across the top surface of the photonic chip and the top surface of the electrical chip and connects the photonic chip with the electrical chip. Moreover, the photonic chip includes an exposed optical interface for transmitting optical signals between the photonic chip and an external optical device.

公开(公告)号：US11831093B2

公开(公告)日：2023-11-28

申请号：US17645195

申请日：2021-12-20

Applicant: Cisco Technology, Inc.

Inventor： Matthew J. Traverso ,  Sandeep Razdan ,  Joyce J. M. Peternel

IPC: H01R12/70 ,  G02B6/38

CPC classification number: H01R12/7005 ,  G02B6/3817

Abstract: An apparatus includes a substrate, a frame, and a socket. The frame defines a slot. The frame is coupled to the substrate such that the slot is aligned with an attachment location on the substrate. The socket receives a first device. The socket aligns with the attachment location on the substrate when the socket is inserted in the slot.

公开(公告)号：US11762155B2

公开(公告)日：2023-09-19

申请号：US17445914

申请日：2021-08-25

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. Patel ,  Matthew J. Traverso ,  Sandeep Razdan ,  Aparna R. Prasad

IPC: G02B6/42

CPC classification number: G02B6/423 ,  G02B6/4202

Abstract: Embodiments herein describe an optical system that includes a photonic integrated circuit (PIC) bonded to a package containing an electrical integrated circuit (EIC). However, this bond can prevent an edge coupler from optically aligning an optical fiber to an edge of the PIC in order to transfer optical signals. To provide room for the edge coupler, the PIC is arranged to overhang the package containing the EIC so that the package does not interfere with the ability of the edge coupler to align with the side or edge of the PIC. In this manner, an optical fiber can be optically aligned (e.g., butt coupled) to the edge of the PIC rather than having to use a grating coupler or some other less efficient optical coupling in order to transfer optical signals between the PIC and the optical fiber.