- 专利标题: Hybrid digital linear and switched capacitor voltage regulator
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申请号: US17714969申请日: 2022-04-06
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公开(公告)号: US11757357B2公开(公告)日: 2023-09-12
- 发明人: Takao Oshita , Fabrice Paillet , Rinkle Jain , Jad Rizk , Danny Bronstein , Ahmad Arnaot
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 分案原申请号: US16563495 2019.09.06
- 主分类号: H02M3/07
- IPC分类号: H02M3/07 ; G06F1/3234 ; H03K5/24 ; H02M1/00
摘要:
An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
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