Invention Grant
- Patent Title: Techniques for handling cache coherency traffic for contended semaphores
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Application No.: US17547148Application Date: 2021-12-09
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Publication No.: US11768771B2Publication Date: 2023-09-26
- Inventor: John M. King , Gregory W. Smaus
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Volpe Koenig
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0808 ; G06F12/0815 ; G06F12/0844 ; G06F12/0877 ; G06F9/52

Abstract:
The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.
Public/Granted literature
- US20220100662A1 TECHNIQUES FOR HANDLING CACHE COHERENCY TRAFFIC FOR CONTENDED SEMAPHORES Public/Granted day:2022-03-31
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