Invention Grant
- Patent Title: Sequential SLC read optimization
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Application No.: US17673302Application Date: 2022-02-16
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Publication No.: US11776615B2Publication Date: 2023-10-03
- Inventor: Tomoko Ogura Iwasaki , Tracy D. Evans , Avani F. Trivedi , Aparna U. Limaye , Jianmin Huang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C11/408
- IPC: G11C11/408 ; G06F12/02 ; G11C11/4074

Abstract:
Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.
Public/Granted literature
- US20220172769A1 SEQUENTIAL SLC READ OPTIMIZATION Public/Granted day:2022-06-02
Information query
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