- 专利标题: FPGA device forming network-on-chip by using silicon connection layer
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申请号: US17294985申请日: 2020-12-30
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公开(公告)号: US11776915B2公开(公告)日: 2023-10-03
- 发明人: Jicong Fan , Yanfeng Xu , Yueer Shan , Hua Yan , Yanfei Zhang
- 申请人: WUXI ESIONTECH CO., LTD.
- 申请人地址: CN Jiangsu
- 专利权人: WUXI ESIONTECH CO., LTD.
- 当前专利权人: WUXI ESIONTECH CO., LTD.
- 当前专利权人地址: CN Jiangsu
- 代理机构: Hamre, Schumann, Mueller & Larson, P.C.
- 优先权: CN 2010620258.7 2020.07.01
- 国际申请: PCT/CN2020/141194 2020.12.30
- 国际公布: WO2022/001064A 2022.01.06
- 进入国家日期: 2021-05-18
- 主分类号: H01L23/538
- IPC分类号: H01L23/538 ; H01L25/065 ; H01L23/00 ; H01L23/535 ; G06F30/394 ; G06F30/39 ; H03K19/17736 ; G06F15/78 ; G06F30/347 ; H10B80/00
摘要:
The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.
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