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公开(公告)号：US12095460B2
公开(公告)日：2024-09-17
申请号：US17955578
申请日：2022-09-29
发明人： Yueer Shan , Zhengzhou Cao , Wenhu Xie , Yanfei Zhang , Ting Jiang , Bo Tu
IPC分类号： H03K19/20 , H03K19/17748
CPC分类号： H03K19/17748 , H03K19/20
摘要： A configuration circuit of a flash FPGA for realizing external monitoring and configuration is provided. In the configuration circuit, a positive high-voltage output terminal of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the positive high-voltage output terminal of a positive high-voltage charge pump is further configured as a positive output end of a voltage supply circuit. A negative high-voltage output terminal of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the negative high-voltage output terminal of a negative high-voltage charge pump is further configured as a negative output end of the voltage supply circuit. Based on a received mode adjustment signal, a mode control circuit controls to enter an external monitoring mode or an external configuration mode.
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公开(公告)号：US12099377B2
公开(公告)日：2024-09-24
申请号：US17955581
申请日：2022-09-29
发明人： Chenguang Kuang , Yanfei Zhang , Boyin Chen , Jicong Fan
IPC分类号： G06F1/08 , G06F1/10 , G06F30/396
CPC分类号： G06F1/08 , G06F1/10 , G06F30/396
摘要： A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.
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公开(公告)号：US12119069B2
公开(公告)日：2024-10-15
申请号：US17955579
申请日：2022-09-29
发明人： Zhengzhou Cao , Jie Zhu , Yanfei Zhang , Jing Sun , Zhenkai Ji , Zhengnan Ding
CPC分类号： G11C17/18 , G11C7/1069 , G11C7/1093 , G11C7/12
摘要： In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.
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公开(公告)号：US12087377B2
公开(公告)日：2024-09-10
申请号：US17903061
申请日：2022-09-06
发明人： Zhengzhou Cao , Yueer Shan , Yanfei Zhang , Yan Jiang , Yuting Xu , Hui Xu
摘要： In an anti-fuse programming control circuit based on a master-slave charge pump structure, a master charge pump module obtains an external voltage and is connected to a plurality of slave charge pump modules. Each slave charge pump module is connected to an anti-fuse bank. The distance between the layout position of each slave charge pump module and the layout position of the connected anti-fuse bank does not exceed a predetermined distance. Based on a programming voltage output by each slave charge pump module to the connected anti-fuse bank, the feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module. Based on the feedback signal corresponding to each slave charge pump module, the master charge pump module adjusts a master drive signal provided to the slave charge pump module to stabilize the programming voltage output by the slave charge pump module.
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5.发明授权公开(公告)号：US12009307B2
公开(公告)日：2024-06-11
申请号：US17421460
申请日：2020-12-30
发明人： Yueer Shan , Yanfeng Xu , Jicong Fan , Yanfei Zhang , Hua Yan
IPC分类号： H01L23/00 , H01L23/538 , H01L25/065 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/17796
CPC分类号： H01L23/5381 , H01L23/5386 , H01L24/16 , H01L25/0652 , H03K19/17728 , H03K19/17744 , H03K19/1776 , H03K19/17764 , H03K19/17796 , H01L2224/16145 , H01L2224/16227 , H01L2224/16238 , H01L2924/14211 , H01L2924/1424 , H01L2924/1431 , H01L2924/14335 , H01L2924/30105 , H01L2924/30107 , H01L2924/37001
摘要： The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.
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公开(公告)号：US11776915B2
公开(公告)日：2023-10-03
申请号：US17294985
申请日：2020-12-30
发明人： Jicong Fan , Yanfeng Xu , Yueer Shan , Hua Yan , Yanfei Zhang
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00 , H01L23/535 , G06F30/394 , G06F30/39 , H03K19/17736 , G06F15/78 , G06F30/347 , H10B80/00
CPC分类号： H01L23/5386 , G06F15/7825 , G06F30/347 , G06F30/39 , G06F30/394 , H01L23/535 , H01L24/16 , H01L25/0652 , H03K19/17736 , H03K19/17744 , H01L2224/16146 , H01L2224/16227 , H01L2224/16238 , H01L2924/1431 , H01L2924/14361 , H10B80/00
摘要： The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.
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公开(公告)号：US11750510B2
公开(公告)日：2023-09-05
申请号：US17236400
申请日：2021-04-21
发明人： Yanfeng Xu , Yueer Shan , Jicong Fan , Yanfei Zhang , Hua Yan
IPC分类号： H04L45/58 , H04L49/109
CPC分类号： H04L45/583 , H04L49/109
摘要： The present disclosure discloses an FPGA device for implementing a network-on-chip transmission bandwidth expansion function, and relates to the technical field of FPGAs. When a predefined functional module with built-in hardcore IP nodes is integrated in an FPGA bare die, soft-core IP nodes are configured and formed by using logical resource modules in the FPGA bare die and are connected to the hardcore IP nodes to form an NOC network structure, so as to increase nodes and expand the transmission bandwidth of the predefined functional module. On the other hand, the soft-core IP nodes can be additionally connected to input and output signals in the predefined functional module and also can expand the transmission bandwidth of the predefined functional module.
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