Invention Grant
- Patent Title: Gate structures for stacked semiconductor devices
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Application No.: US17461329Application Date: 2021-08-30
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Publication No.: US11776960B2Publication Date: 2023-10-03
- Inventor: Mrunal Abhijith Khaderbad , Sathaiya Mahaveer Dhanyakumar , Huicheng Chang , Keng-Chu Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238

Abstract:
The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.
Public/Granted literature
- US20230062940A1 Gate Structures for Stacked Semiconductor Devices Public/Granted day:2023-03-02
Information query
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