Invention Grant
- Patent Title: Semiconductor device having a node capping pattern and a gate capping pattern
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Application No.: US17185102Application Date: 2021-02-25
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Publication No.: US11778801B2Publication Date: 2023-10-03
- Inventor: Sung Hun Jung , Heon Jong Shin , Min Chan Gwak , Sung Moon Lee , Jeong Ki Hwang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-Do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR 20200087200 2020.07.15
- Main IPC: H10B10/00
- IPC: H10B10/00 ; H01L23/528 ; H01L21/768

Abstract:
A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.
Public/Granted literature
- US20220020753A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2022-01-20
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