公开(公告)号：US20240372002A1

公开(公告)日：2024-11-07

申请号：US18775240

申请日：2024-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung In Choi ,  Hae Jun Yu ,  Sung Hun Jung

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/08

Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.

公开(公告)号：US11778801B2

公开(公告)日：2023-10-03

申请号：US17185102

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun Jung ,  Heon Jong Shin ,  Min Chan Gwak ,  Sung Moon Lee ,  Jeong Ki Hwang

IPC: H10B10/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H10B10/12 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/528 ,  H10B10/125

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US12080796B2

公开(公告)日：2024-09-03

申请号：US17462026

申请日：2021-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung In Choi ,  Hae Jun Yu ,  Sung Hun Jung

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L23/5283 ,  H01L29/0847

Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.