Invention Grant
- Patent Title: Pipeline protection for CPUs with save and restore of intermediate results
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Application No.: US17688260Application Date: 2022-03-07
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Publication No.: US11789742B2Publication Date: 2023-10-17
- Inventor: Timothy D. Anderson , Duc Bui , Joseph Zbiciak , Reid E. Tatge
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Frank D. Cimino
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.
Public/Granted literature
- US20220188121A1 Pipeline Protection for CPUs With Save and Restore of Intermediate Results Public/Granted day:2022-06-16
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