公开(公告)号：US20240411703A1

公开(公告)日：2024-12-12

申请号：US18813178

申请日：2024-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

公开(公告)号：US12067396B2

公开(公告)日：2024-08-20

申请号：US17557162

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F9/3858 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.

公开(公告)号：US11900112B2

公开(公告)日：2024-02-13

申请号：US17705453

申请日：2022-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Duc Bui

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3013 ,  G06F9/30043 ,  G06F9/30105

Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

公开(公告)号：US20240036736A1

公开(公告)日：2024-02-01

申请号：US18361159

申请日：2023-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A system for handling requests that includes a set of memory banks coupled to a memory controller which comprises a set of read queues, including a read queue currently designated as the priority read queue. The memory controller loads read requests from an associated processor into the set of read queues. To process the read requests, the memory controller is configured to schedule the read requests of the priority read queue based on an availability of the associated memory bank, and if not in the priority read queue, also based on whether the read requests conflict with a recently scheduled read request from the priority read queue. Upon an execution of a read request from the priority read queue, the memory controller designates a different one of the set of read queues as the priority read queue, if the read request was at a front of the priority read queue.

公开(公告)号：US11782718B2

公开(公告)日：2023-10-10

申请号：US17216821

申请日：2021-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Kai Chirca ,  Timothy D. Anderson ,  Duc Bui ,  Abhijeet A. Chachad ,  Son Hung Tran

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345 ,  G06F12/0811

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3867 ,  G06F9/3877 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F11/10 ,  G06F12/0811 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

公开(公告)号：US11442709B2

公开(公告)日：2022-09-13

申请号：US16983429

申请日：2020-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

公开(公告)号：US20210240634A1

公开(公告)日：2021-08-05

申请号：US17237391

申请日：2021-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

公开(公告)号：US20200371888A1

公开(公告)日：2020-11-26

申请号：US16988500

申请日：2020-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/36 ,  G06F11/07

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US10713174B2

公开(公告)日：2020-07-14

申请号：US15384345

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F12/08 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

公开(公告)号：US10203958B2

公开(公告)日：2019-02-12

申请号：US15635409

申请日：2017-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F9/312 ,  G06F9/34 ,  G06F12/12 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.