A tiling display apparatus includes a plurality of display modules connected to one another to configure a screen, a set board configured to output an input data enable signal and image data synchronized therewith to one of the plurality of display modules, and first to Nth (where N is a natural number of 3 or more) timing controllers configured for the plurality of display modules, the first to Nth timing controllers are sequentially connected to one another in a first direction through a first interface line based on a cascading scheme and configured to receive the input data enable signal and the image data at different timings which are sequentially delayed and synchronize a display time of the image data on the basis of an independently generated output data enable signal.