Invention Grant
- Patent Title: Circuit for generating and trimming phases for memory cell read operations
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Application No.: US18175375Application Date: 2023-02-27
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Publication No.: US11798603B2Publication Date: 2023-10-24
- Inventor: Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
- Applicant: STMICROELECTRONICS S.r.l. , STMicroelectronics International N.V.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.r.l.,STMicroelectronics International N.V.
- Current Assignee: STMICROELECTRONICS S.r.l.,STMicroelectronics International N.V.
- Current Assignee Address: IT Agrate Brianza; CH Geneva
- Agency: Seed IP Law Group LLP
- Main IPC: G11C7/12
- IPC: G11C7/12 ; G11C7/06 ; G11C11/4094 ; G11C11/4091 ; G11C7/22

Abstract:
A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
Public/Granted literature
- US20230206971A1 CIRCUIT FOR GENERATING AND TRIMMING PHASES FOR MEMORY CELL READ OPERATIONS Public/Granted day:2023-06-29
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