A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising: providing a multi-processor having a plurality of processing units; receiving a trim command and a logical block address (LBA) range sent from the host device; separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range; using the processing units to execute the N threads individually; and maximizing a number of execution cycles during which the processing units are busy.