Method and apparatus for performing access management of memory device with aid of serial number assignment timing control

    公开(公告)号:US11899977B2

    公开(公告)日:2024-02-13

    申请号:US17691137

    申请日:2022-03-10

    Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

    FLASH MEMORY SCHEME CAPABLE OF DECREASING WAITING TIME OF TRIM COMMAND

    公开(公告)号:US20230229312A1

    公开(公告)日:2023-07-20

    申请号:US17578380

    申请日:2022-01-18

    CPC classification number: G06F3/0611 G06F3/0659 G06F3/0679

    Abstract: A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising: providing a multi-processor having a plurality of processing units; receiving a trim command and a logical block address (LBA) range sent from the host device; separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range; using the processing units to execute the N threads individually; and maximizing a number of execution cycles during which the processing units are busy.

    METHOD AND APPARATUS FOR PERFORMING ACCESS MANAGEMENT OF MEMORY DEVICE WITH AID OF SERIAL NUMBER ASSIGNMENT TIMING CONTROL

    公开(公告)号:US20230289097A1

    公开(公告)日:2023-09-14

    申请号:US17691137

    申请日:2022-03-10

    Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

    Flash memory scheme capable of decreasing waiting time of trim command

    公开(公告)号:US11809711B2

    公开(公告)日:2023-11-07

    申请号:US17578380

    申请日:2022-01-18

    CPC classification number: G06F3/0611 G06F3/0659 G06F3/0679 G06F2212/7205

    Abstract: A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising: providing a multi-processor having a plurality of processing units; receiving a trim command and a logical block address (LBA) range sent from the host device; separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range; using the processing units to execute the N threads individually; and maximizing a number of execution cycles during which the processing units are busy.

    Flash Storage Devices Executing ECC in Parallel and Methods Thereof

    公开(公告)号:US20190050167A1

    公开(公告)日:2019-02-14

    申请号:US15922669

    申请日:2018-03-15

    Abstract: A storage device receiving an external instruction from a host includes a plurality of flash memory spaces and a controller. The controller receives the external instruction, queues the external instruction in a first command queue, translates the external instruction into a plurality of operation commands, and sequentially executes the operation commands to respectively operate the flash memory spaces. The controller further gives an identity code to at least one specific operation command to track the execution result of the specific operation command.

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