Invention Grant
- Patent Title: Implementing mapping data structures to minimize sequentially written data accesses
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Application No.: US18105327Application Date: 2023-02-03
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Publication No.: US11836076B2Publication Date: 2023-12-05
- Inventor: Naveen Bolisetty
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Priority: IN 2141036475 2021.08.12
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/02 ; G06F12/1045 ; G06F3/06 ; G06F12/1009 ; G06F12/1027

Abstract:
A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including storing, on a volatile memory device, logical-to-physical (L2P) mapping data corresponding to sequentially written data, determining whether an L2P update criterion is satisfied, and in response to determining that the L2P update criterion is satisfied, updating an L2P mapping data structure based on the L2P mapping data. The L2P mapping data structure maintains an initial logical translation unit (LTU) of the sequentially written data, and a length of the sequentially written data from the initial LTU.
Public/Granted literature
- US20230185712A1 IMPLEMENTING MAPPING DATA STRUCTURES TO MINIMIZE SEQUENTIALLY WRITTEN DATA ACCESSES Public/Granted day:2023-06-15
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