Invention Grant
- Patent Title: Semiconductor package with improved interposer structure
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Application No.: US17400729Application Date: 2021-08-12
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Publication No.: US11848265B2Publication Date: 2023-12-19
- Inventor: Yi-Wen Wu , Techi Wong , Po-Hao Tsai , Po-Yao Chuang , Shih-Ting Hung , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/00 ; H01L23/48 ; H01L23/31 ; H01L23/528 ; H01L21/56

Abstract:
A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.
Public/Granted literature
- US20210375755A1 SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE Public/Granted day:2021-12-02
Information query
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