公开(公告)号：US11637054B2

公开(公告)日：2023-04-25

申请号：US17010849

申请日：2020-09-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ting Hung ,  Meng-Liang Lin ,  Shin-Puu Jeng ,  Yi-Wen Wu ,  Po-Yao Chuang

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L25/16

摘要： A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

公开(公告)号：US11600575B2

公开(公告)日：2023-03-07

申请号：US17373016

申请日：2021-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Lin ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Chuang

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L21/768

摘要： A method for forming a chip package structure is provided. The method includes forming a conductive pad over a carrier substrate. The method includes forming a substrate layer over the carrier substrate, wherein the conductive pad is embedded in the substrate layer, and the substrate layer includes fibers. The method includes forming a through hole in the substrate layer and exposing the conductive pad. The method includes forming a conductive pillar in the through hole. The method includes forming a recess in the substrate layer. The method includes disposing a chip in the recess. The method includes forming a molding layer in the recess. The method includes forming a redistribution structure over the substrate layer, the conductive pillar, the molding layer, and the chip. The method includes removing the carrier substrate.

公开(公告)号：US20230067914A1

公开(公告)日：2023-03-02

申请号：US17462000

申请日：2021-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Liang Lin ,  Po-Yao Chuang ,  Te-Chi Wong ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

公开(公告)号：US11527474B2

公开(公告)日：2022-12-13

申请号：US17034805

申请日：2020-09-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC分类号： H01L23/522 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768

摘要： In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

公开(公告)号：US11164754B2

公开(公告)日：2021-11-02

申请号：US16371917

申请日：2019-04-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao Tsai ,  Ming-Chih Yew ,  Chia-Kuei Hsu ,  Shin-Puu Jeng ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Shih-Ting Hung ,  Po-Yao Lin

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/522 ,  H01L25/10 ,  H01L23/538 ,  H01L23/367 ,  H01L23/13 ,  H01L23/31 ,  H01L23/482 ,  H01L23/488

摘要： Embodiments include forming an interposer having reinforcing structures disposed in a core layer of the interposer. The interposer may be attached to a package device by electrical connectors. The reinforcing structures provide rigidity and thermal dissipation for the package device. Some embodiments may include an interposer with an opening in an upper core layer of the interposer to a recessed bond pad. Some embodiments may also use connectors between the interposer and the package device where a solder material connected to the interposer surrounds a metal pillar connected to the package device.

公开(公告)号：US10790162B2

公开(公告)日：2020-09-29

申请号：US16207850

申请日：2018-12-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC分类号： H01L21/56 ,  H01L23/522 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768

摘要： In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

公开(公告)号：US20190355680A1

公开(公告)日：2019-11-21

申请号：US16185749

申请日：2018-11-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Yao Chuang ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC分类号： H01L23/66 ,  H01L23/498 ,  H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22

摘要： A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.

公开(公告)号：US12074104B2

公开(公告)日：2024-08-27

申请号：US18064417

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC分类号： H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/5226 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/14 ,  H01L2224/02372 ,  H01L2224/0401

摘要： In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

公开(公告)号：US11848265B2

公开(公告)日：2023-12-19

申请号：US17400729

申请日：2021-08-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Wen Wu ,  Techi Wong ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Shih-Ting Hung ,  Shin-Puu Jeng

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

CPC分类号： H01L23/5226 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/73203

摘要： A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.

公开(公告)号：US20230386956A1

公开(公告)日：2023-11-30

申请号：US18363742

申请日：2023-08-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Liang Lin ,  Po-Yao Chuang ,  Te-Chi Wong ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

CPC分类号： H01L23/3192 ,  H01L21/563 ,  H01L21/561 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/73 ,  H01L23/481 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2224/16227 ,  H01L2224/32225

摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.