Invention Grant
- Patent Title: Chip scale package structure and method of forming the same
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Application No.: US17989498Application Date: 2022-11-17
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Publication No.: US11854784B2Publication Date: 2023-12-26
- Inventor: Yen-Yao Chi , Nai-Wei Liu , Ta-Jen Yu , Tzu-Hung Lin , Wen-Sung Hsu , Shih-Chin Lin
- Applicant: MediaTek Inc.
- Applicant Address: TW Hsin-Chu
- Assignee: MediaTek Inc.
- Current Assignee: MediaTek Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: Wolf, Greenfield & Sacks, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/31 ; H01L23/00 ; H01L21/56 ; H01L23/29

Abstract:
A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
Public/Granted literature
- US20230073399A1 CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME Public/Granted day:2023-03-09
Information query
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