公开(公告)号：US20240047427A1

公开(公告)日：2024-02-08

申请号：US18489814

申请日：2023-10-18

Applicant: MediaTek Inc.

Inventor： Yi-Lin Tsai ,  Wen-Sung Hsu ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L23/49822

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.

公开(公告)号：US11854930B2

公开(公告)日：2023-12-26

申请号：US17901849

申请日：2022-09-01

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L21/563 ,  H01L24/16 ,  H01L25/0655 ,  H01L2924/3511

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

公开(公告)号：US11742564B2

公开(公告)日：2023-08-29

申请号：US17321914

申请日：2021-05-17

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Yen-Yao Chi ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/38 ,  H01Q9/16

CPC classification number: H01Q1/2283 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/20 ,  H01Q1/38 ,  H01Q9/16 ,  H01L2223/6677 ,  H01L2224/211 ,  H01L2224/221

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

公开(公告)号：US20220352084A1

公开(公告)日：2022-11-03

申请号：US17748308

申请日：2022-05-19

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/498 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US11469201B2

公开(公告)日：2022-10-11

申请号：US16721475

申请日：2019-12-19

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US11469152B2

公开(公告)日：2022-10-11

申请号：US17035719

申请日：2020-09-29

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

公开(公告)号：US20210217707A1

公开(公告)日：2021-07-15

申请号：US17111456

申请日：2020-12-03

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Shih-Chao Chiu ,  Wen-Sung Hsu ,  Sang-Mao Chiu ,  Chi-Yuan Chen ,  Yao-Pang Hsu

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a substrate component having a first surface, a second surface opposite to the first surface, and a sidewall surface extending between the first surface and the second surface; a re-distribution layer (RDL) structure disposed on the first surface and electrically connected to the first surface through first connecting elements comprising solder bumps or balls; a plurality of ball grid array (BGA) balls mounted on the second surface of the substrate component; and at least one integrated circuit die mounted on the RDL structure through second connecting elements.

公开(公告)号：US10978406B2

公开(公告)日：2021-04-13

申请号：US16007032

申请日：2018-06-13

Applicant: MEDIATEK INC.

Inventor： Hung-Jen Chang ,  Jen-Chuan Chen ,  Hsueh-Te Wang ,  Wen-Sung Hsu

IPC: H01L23/552 ,  H01L25/065 ,  H01L25/16 ,  H01L21/3205 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/285

Abstract: A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate has a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a patterned conductive layer in a level of the insulating layer. The patterned conductive layer includes conductors in and along the edge region. The edge region is partially exposed from the conductors, as viewed from a top-view perspective. The conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductors.

公开(公告)号：US10573616B2

公开(公告)日：2020-02-25

申请号：US15194658

申请日：2016-06-28

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US20200013735A1

公开(公告)日：2020-01-09

申请号：US16452395

申请日：2019-06-25

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Yen-Yao Chi ,  Yeh-Chun Kao ,  Shih-Huang Yeh ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. A second RDL structure is formed on and electrically coupled to an active surface of the semiconductor die. A ground layer is formed in the first RDL structure. A first molding compound layer is formed on the first RDL structure. A first antenna includes a first antenna element formed in the second RDL structure and a second antenna element formed on the first molding compound layer. Each of the first antenna element and the second antenna element has a first portion overlapping the semiconductor die as viewed from a top-view perspective.