- Patent Title: Wafer level stacked structures having integrated passive features
-
Application No.: US17875205Application Date: 2022-07-27
-
Publication No.: US11854958B2Publication Date: 2023-12-26
- Inventor: Marco Francesco Aimi , Joseph Alfred Iannotti , Joleyn Eileen Brewer
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Armstrong Teasdale LLP
- The original application number of the division: US16666016 2019.10.28
- Main IPC: H01L21/48
- IPC: H01L21/48 ; B81C1/00 ; B81C3/00 ; H01L21/60 ; H01L23/522 ; B81B7/02 ; B81B7/00 ; H01L49/02 ; H01L23/64

Abstract:
A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.
Public/Granted literature
- US20220367339A1 WAFER LEVEL STACKED STRUCTURES HAVING INTEGRATED PASSIVE FEATURES Public/Granted day:2022-11-17
Information query
IPC分类: