- Patent Title: Method of forming a semiconductor memory device with remaining upper electrode layer covering only logic circuit region on magnetic tunneling junction stack layer
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Application No.: US17343768Application Date: 2021-06-10
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Publication No.: US11856863B2Publication Date: 2023-12-26
- Inventor: Hui-Lin Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN 2110538653.5 2021.05.18
- Main IPC: H10N50/01
- IPC: H10N50/01 ; H10B61/00 ; H10N50/10 ; H10N50/85

Abstract:
A method of forming a semiconductor memory device is disclosed. A top electrode layer is formed on the MTJ stack layer. A patterned buffer layer is formed to cover only the logic circuit region. A hard mask layer is formed on the top electrode layer and the patterned buffer layer. A patterned resist layer is formed on the hard mask layer. A first etching process is performed to etch the hard mask layer and the top electrode layer not covered by the patterned resist layer in the memory region and the hard mask layer, the patterned buffer layer and the top electrode layer in the logic circuit region, thereby forming a top electrode on the MTJ stack layer in the memory region and a remaining top electrode layer covering only the logic circuit region on the MTJ stack layer.
Public/Granted literature
- US20220376173A1 METHOD OF FORMING A SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2022-11-24
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