The subject matter described herein relates to a semiconductor circuit arrangement with a semiconductor substrate with an integrated Hall sensor circuit. During a first clock phase PHspin1 a first electrical voltage signal ±VHallout(PHspin1) or ±VHallbias(PHspin1) can be generated in the Hall effect region that has a first dependency on a mechanical stress of the semiconductor substrate. During a second clock phase PHspin2 a second electrical voltage signal ±VHallout(PHspin2) or ±VHallbias(PHspin2) can be generated in the Hall effect region that has a second dependency on a mechanical stress of the semiconductor substrate. The semiconductor circuit arrangement is designed to ascertain a specific mechanical stress component based on a combination of the first electrical voltage signal ±VHallout(PHspin1) or ±VHallbias(PHspin1) and of the second electrical voltage signal ±VHallout(PHspin2) or ±VHallbias(PHspin2).