Invention Grant
- Patent Title: Device isolator with reduced parasitic capacitance
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Application No.: US17398292Application Date: 2021-08-10
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Publication No.: US11869933B2Publication Date: 2024-01-09
- Inventor: Raja Selvaraj , Anant Shankar Kamath , Byron Lovell Williams , Thomas D. Bonifield , John Kenneth Arch
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Valerie M. Davis; Frank D. Cimino
- The original application number of the division: US16228817 2018.12.21
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L27/06 ; H01L21/761 ; H01L23/522 ; H01L23/528 ; H01L23/00 ; H01L49/02 ; H01L21/265

Abstract:
Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
Public/Granted literature
- US20210367030A1 DEVICE ISOLATOR WITH REDUCED PARASITIC CAPACITANCE Public/Granted day:2021-11-25
Information query
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