公开(公告)号：US20160300907A1

公开(公告)日：2016-10-13

申请号：US14680211

申请日：2015-04-07

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/761 ,  H01L21/265 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

Abstract translation: 具有降低的有效寄生电容的集成电路的隔离器结构。 公开的实施例包括具有形成电容器或电感变压器的并联导电元件的隔离器结构，覆盖包括形成在第二导电类型的槽区域内的第一导电类型的阱区的半导体结构。 槽区被掺杂区域和第一导电类型的掩埋掺杂层围绕，形成与衬底串联的多个二极管。 串联二极管的结电容具有降低隔离器明显的寄生电容的作用。

公开(公告)号：US11869933B2

公开(公告)日：2024-01-09

申请号：US17398292

申请日：2021-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L21/265

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US10546780B2

公开(公告)日：2020-01-28

申请号：US15343557

申请日：2016-11-04

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L23/18 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02

Abstract: An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US10186576B2

公开(公告)日：2019-01-22

申请号：US15714682

申请日：2017-09-25

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L21/76 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L21/761 ,  H01L21/265 ,  H01L23/528 ,  H01L23/00

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator

公开(公告)号：US09806148B2

公开(公告)日：2017-10-31

申请号：US14680211

申请日：2015-04-07

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L49/02 ,  H01L21/265 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US20210367030A1

公开(公告)日：2021-11-25

申请号：US17398292

申请日：2021-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L49/02 ,  H01L21/761 ,  H01L21/265 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US11107883B2

公开(公告)日：2021-08-31

申请号：US16228817

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L29/06 ,  H01L49/02 ,  H01L21/761 ,  H01L21/265

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US20190148486A1

公开(公告)日：2019-05-16

申请号：US16228817

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L21/761 ,  H01L27/06 ,  H01L21/265

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US20180068894A1

公开(公告)日：2018-03-08

申请号：US15343557

申请日：2016-11-04

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L29/06 ,  H01L23/00 ,  H01L23/18

Abstract: An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US11545480B2

公开(公告)日：2023-01-03

申请号：US16222670

申请日：2018-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sachin Ishwar Gojagoji ,  Raja Selvaraj ,  Jayateerth Pandurang Mathad ,  Sujay Kumar

IPC: H01L27/08 ,  H01L27/02 ,  H01L49/02 ,  H01L27/10 ,  H01L27/118 ,  H01L27/11

Abstract: An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.