• Patent Title: Process for collectively fabricating a plurality of semiconductor structures
  • Application No.: US17291957
    Application Date: 2019-10-24
  • Publication No.: US11876073B2
    Publication Date: 2024-01-16
  • Inventor: David Sotta
  • Applicant: Soitec
  • Applicant Address: FR Bernin
  • Assignee: SOITEC
  • Current Assignee: SOITEC
  • Current Assignee Address: FR Bernin
  • Agency: TraskBritt
  • Priority: FR 60294 2018.11.08
  • International Application: PCT/FR2019/052538 2019.10.24
  • International Announcement: WO2020/094944A 2020.05.14
  • Date entered country: 2021-05-06
  • Main IPC: H01L21/02
  • IPC: H01L21/02 H01L23/00 H01L33/00 H01L21/20 H01L25/065 H01L25/00
Process for collectively fabricating a plurality of semiconductor structures
Abstract:
A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.
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