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公开(公告)号：US11245050B2
公开(公告)日：2022-02-08
申请号：US16487037
申请日：2018-02-26
Applicant: Soitec
Inventor： David Sotta
IPC: H01L33/12 , H01L33/00 , H01L21/02 , H01L21/324
Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
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2.发明申请公开(公告)号：US20210351318A1
公开(公告)日：2021-11-11
申请号：US17385138
申请日：2021-07-26
Applicant: Soitec
Inventor： David Sotta
IPC: H01L33/00 , H01L21/02 , H01L21/324 , H01L33/12
Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
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公开(公告)号：US11876073B2
公开(公告)日：2024-01-16
申请号：US17291957
申请日：2019-10-24
Applicant: Soitec
Inventor： David Sotta
CPC classification number: H01L24/94 , H01L21/02639 , H01L21/2007 , H01L25/0655 , H01L25/50 , H01L33/0093 , H01L2224/94
Abstract: A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.
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4.发明申请公开(公告)号：US20190228967A1
公开(公告)日：2019-07-25
申请号：US16337206
申请日：2017-09-21
Applicant: Soitec
Inventor： David Sotta , Jean-Marc Bethoux , Oleg Kononchuk
IPC: H01L21/02
Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.
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5.发明授权公开(公告)号：US11735685B2
公开(公告)日：2023-08-22
申请号：US17385138
申请日：2021-07-26
Applicant: Soitec
Inventor： David Sotta
IPC: H01L21/02 , H01L33/00 , H01L21/324 , H01L33/12
CPC classification number: H01L33/007 , H01L21/02002 , H01L21/0254 , H01L21/02389 , H01L21/3245 , H01L33/0075 , H01L33/12
Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
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Patent Agency Ranking
公开(公告)号：US20210210653A1
公开(公告)日：2021-07-08
申请号：US16069469
申请日：2018-03-14
Applicant: Soitec
Inventor： David Sotta , Olivier Ledoux , Olivier Bonnin , Jean-Marc Bethoux , Morgane Logiou , Raphaél Caulmilone
IPC: H01L33/00
Abstract: A growth substrate for forming optoelectronic devices comprises a growth medium and, arranged on the growth medium, a first group of crystalline semiconductor islands having a first lattice parameter and a second group of crystalline semiconductor islands having a second lattice parameter that is different from the first. Methods may be used to manufacture such growth substrates. The methods may be used to provide a monolithic micro-panel or light-emitting diodes or a micro-display screen.
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公开(公告)号：US20180269253A1
公开(公告)日：2018-09-20
申请号：US15491827
申请日：2017-04-19
Applicant: Soitec
Inventor： David Sotta , Olivier Ledoux , Olivier Bonnin
Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters comprises providing a substrate including a medium, a flow layer disposed on the medium, and a plurality of strained crystalline semiconductor islands having an initial lattice parameter arranged on the flow layer. The strained semiconductor islands are selectively treated so as to form a first group of strained islands having a first lateral expansion potential, and a second group of strained islands having a second lateral expansion potential that is different from the first lateral expansion potential. The substrate is heat treated at a temperature at or above a glass transition temperature of the flow layer to cause differentiated relaxation of the islands of the first and second groups, such that a lattice parameter of the first group of relaxed islands differs from a lattice parameter of the second group of relaxed islands.
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8.发明申请公开(公告)号：US20220140190A1
公开(公告)日：2022-05-05
申请号：US17435014
申请日：2020-02-25
Applicant: Soitec
Inventor： David Sotta , Mariia Rozhavskaia , Benjamin Daminlano
Abstract: An optoelectronic semiconductor structure comprises an InGaN-based active layer disposed between an n-type injection layer and a p-type injection layer, the p-type injection layer comprising a first InGaN layer having a thickness between 50 and 350 nm and, disposed on the first layer, a second layer having a GaN surface portion.
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9.发明授权公开(公告)号：US11295950B2
公开(公告)日：2022-04-05
申请号：US16337206
申请日：2017-09-21
Applicant: Soitec
Inventor： David Sotta , Jean-Marc Bethoux , Oleg Kononchuk
IPC: H01L21/02
Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.
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公开(公告)号：US20220005785A1
公开(公告)日：2022-01-06
申请号：US17291957
申请日：2019-10-24
Applicant: Soitec
Inventor： David Sotta
Abstract: A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.
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