- Patent Title: Multi-stage equalizer for inter-symbol interference cancellation
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Application No.: US17978422Application Date: 2022-11-01
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Publication No.: US11876650B2Publication Date: 2024-01-16
- Inventor: Prashant Choudhary , Nanyang Wang
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark H. Whittenberger
- Main IPC: H04L25/03
- IPC: H04L25/03

Abstract:
An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.
Public/Granted literature
- US20230119007A1 Multi-Stage Equalizer for Inter-Symbol Interference Cancellation Public/Granted day:2023-04-20
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