公开(公告)号：US11876650B2

公开(公告)日：2024-01-16

申请号：US17978422

申请日：2022-11-01

Applicant: Cadence Design Systems, Inc.

Inventor： Prashant Choudhary ,  Nanyang Wang

IPC: H04L25/03

CPC classification number: H04L25/03076 ,  H04L25/03318

Abstract: An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.