Invention Grant
- Patent Title: Receiver circuitry having a transistor pair for input voltage clipping
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Application No.: US17698871Application Date: 2022-03-18
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Publication No.: US11881884B2Publication Date: 2024-01-23
- Inventor: Hari Bilash Dubey , Lanka Sasi Rama Subrahmanyam
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H04B1/18
- IPC: H04B1/18 ; H04B1/16

Abstract:
Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal and a reference signal, and generates a first differential signal and a second differential signal. The second stage circuitry receives the first differential signal and the second differential signal, and generates an output signal based on the first differential signal and the second differential signal.
Public/Granted literature
- US20230299802A1 RECEIVER CIRCUITRY HAVING A TRANSISTOR PAIR FOR INPUT VOLTAGE CLIPPING Public/Granted day:2023-09-21
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