A three-dimensional semiconductor memory device may include a first substrate including a cell array region and a cell array contact region, a peripheral circuit structure on the first substrate, and a cell array structure. The cell array structure may include a stack on the peripheral circuit structure, first vertical channel structures and second vertical channel structures on the cell array region and penetrating the stack, and a second substrate connected to the first vertical channel structures and second vertical channel structures. The stack may be between the peripheral circuit structure and the second substrate. The second substrate may include a first portion and a second portion. The first portion may contact the first vertical channel structures and may be doped a first conductivity type. The second portion may contact the second vertical channel structures and may be doped a second conductivity type different from the first conductivity type.