公开(公告)号：US11887951B2

公开(公告)日：2024-01-30

申请号：US17529462

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jiyoung Kim ,  Sanghee Yoon

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device may include a first substrate including a cell array region and a cell array contact region, a peripheral circuit structure on the first substrate, and a cell array structure. The cell array structure may include a stack on the peripheral circuit structure, first vertical channel structures and second vertical channel structures on the cell array region and penetrating the stack, and a second substrate connected to the first vertical channel structures and second vertical channel structures. The stack may be between the peripheral circuit structure and the second substrate. The second substrate may include a first portion and a second portion. The first portion may contact the first vertical channel structures and may be doped a first conductivity type. The second portion may contact the second vertical channel structures and may be doped a second conductivity type different from the first conductivity type.

公开(公告)号：US11930638B2

公开(公告)日：2024-03-12

申请号：US17368029

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jungtae Sung ,  Sanghee Yoon ,  Wooyong Jeon ,  Junyoung Choi ,  Yoonjo Hwang

IPC: H10B43/27 ,  H10B12/00 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B12/50 ,  H10B43/40

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20230084497A1

公开(公告)日：2023-03-16

申请号：US17828170

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Moorym Choi ,  Junyoung Choi ,  Jungtae Sung ,  Sanghee Yoon ,  Wooyong Jeon

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A peripheral circuit structure may be formed on a first surface of a first substrate. A cell array structure may be formed on a first surface of a second substrate and may be attached to the peripheral circuit structure such that those first surfaces face each other. The cell array structure may be formed by forming a back-side via and a preliminary contact pad on the second substrate and forming a semiconductor layer. A hole may be formed to penetrate the semiconductor layer and to expose the preliminary contact pad and may be formed by removing an upper portion of the preliminary contact pad, thereby forming a contact pad separated from the semiconductor layer. The method may further include forming a stack on the semiconductor layer, an insulating layer on the stack, and a contact plug penetrating the insulating layer and connected to the contact pad.