An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.