- 专利标题: Marker-based processor instruction grouping
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申请号: US16713432申请日: 2019-12-13
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公开(公告)号: US11900123B2公开(公告)日: 2024-02-13
- 发明人: Alexander Fuad Ashkar , Manu Rastogi , Harry J. Wise
- 申请人: ADVANCED MICRO DEVICES, INC.
- 申请人地址: US CA Santa Clara
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/38 ; G06T1/20 ; G06F15/80
摘要:
A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.
公开/授权文献
- US20210182072A1 MARKER-BASED PROCESSOR INSTRUCTION GROUPING 公开/授权日:2021-06-17
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